1. Field of the Invention
The present invention relates to a data transmission of a semiconductor device for a high-speed operation and, more specifically, to a circuit for controlling driver strengths of a data and a data strobe in a semiconductor device capable of separately controlling strengths of a data driver and a data strobe driver to adjust a setup and hold time of a system.
2. Discussion of Related Art
With great requirement for a high-speed memory, the minimum data determining time of a data setup/hold time, which was not important in a low-speed memory, tends to be decreased into several hundreds ps unit. This condition gives a large difficulty to determination of data in the high-speed memory. In fact, a DRAM drives data (DQ) and data strobe (DQS) with the same strength, and the DQS is used as a reference signal for receiving the data in a system, which receives the data from the DRAM.
After constructing a system, a data setup/hold time required for the system exists. It is very difficult to change the setup/hold time set once in that system.
In general, in a low-speed memory, a sufficient data transmission is possible with the setup/hold time set once, but in a high-speed memory, problems may be caused. Therefore, in a high-speed memory, it may be required that the setup/hold time is re-adjusted.
If problems occur in a previously set system, strengths of data and data strobe thereof are simultaneously controlled. This conventional art will be described with reference to FIGS. 1 and 2.
In response to input of an extended mode register set (EMRS) code A1 and A2, a control signal is outputted from an EMRS circuit 10. In accordance with this control signal, a driver strength control signal is generated from a driver strength control unit 20. A DQS driver 30 and a DQ driver 40 are simultaneously controlled by means of the driver strength control signal. As a result, DQS and DQ, of which strengths are controlled, are outputted, respectively.
FIG. 2 is a detailed block diagram of the driver strength control unit 20.
For example, output signals of the driver strength control unit 20 are classified into three kinds of signals, that is, a weak signal, a half signal and a full signal.
Since the strength of the DQS driver is not controlled or is controlled together with the strength of the DQ driver, a circuit for controlling the strength of the DQS driver is omitted in FIG. 2.
A data strength control unit comprises a plurality of delay units 310 to 380.
When a weak signal is outputted from the EMRS circuit 10, the data DQ is inputted to the DQ driver 40 only via first to third delay units 310 to 330.
When a half signal is outputted from the EMRS circuit 10, the data DQ is inputted to the DQ driver 40 only via first to sixth delay units 310 to 360.
When a full signal is outputted from the EMRS circuit 10, the data DQ is inputted to the DQ driver 40 via first to eighth delay units 310 to 380.
Conventionally, as described above, the strengths of the DQS driver and the DQ driver could not help being controlled at the same time. That is, since the strengths of the DQS driver and the DQ driver are controlled at the same time and in the same way, arriving times of the DQ and the DQS which is a reference for receiving the data in a party receiving the data could not be adjusted separately. For this reason, the setup/hold time could not be finely controlled in the previously set system.